View SST25WF512_1316993.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
FEATURES:
* Single Voltage Read and Write Operations - 1.65-1.95V * Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 * High Speed Clock Frequency - 40MHz * Superior Reliability - Endurance: 100,000 Cycles - Greater than 100 years Data Retention * Ultra-Low Power Consumption: - Active Read Current: 9 mA (typical @ 20MHz) - Standby Current: 2 A (typical) * Flexible Erase Capability - Uniform 4 KByte sectors - Uniform 32 KByte overlay blocks - Uniform 64 KByte overlay blocks (2 Mbit only) * Fast Erase and Byte-Program: - Chip-Erase Time: 125 ms (typical) - Sector-/Block-Erase Time: 62ms (typical) - Byte-Program Time: 50 S (typical) * Auto Address Increment (AAI) Programming - Decrease total chip programming time over Byte-Program operations * End-of-Write Detection - Software polling the BUSY bit in Status Register - Busy Status readout on SO pin * Reset Pin (RST#) or Programmable Hold Pin (HOLD#) option - Hardware Reset pin as default - Hold pin option to suspend a serial sequence without deselecting the device * Write Protection (WP#) - Enables/Disables the Lock-Down function of the status register * Software Write Protection - Write protection through Block-Protection bits in status register * Temperature Range - Industrial: -40C to +85C * Packages Available - 8-lead SOIC (150 mils) * All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST25WF512/010/020 are members of the Serial Flash 25 Series family and features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SST25WF512/010/020 SPI serial flash memories are manufactured with SST proprietary, highperformance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST25WF512/010/020 devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 1.65-1.95V for SST25WF512/010/020. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST25WF512/010/020 devices are offered in an 8lead, 150 mils SOIC package. See Figure 2 for the pin assignment.
(c)2006 Silicon Storage Technology, Inc. S71328-01-000 02/07 1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Address Buffers and Latches
X - Decoder
SuperFlash Memory
Y - Decoder
Control Logic
I/O Buffers and Data Latches
Serial Interface
CE#
SCK
SI
SO
WP#
RST#/HOLD#
1328 F01.0
Note: In AAI mode, the SO pin functions as an RY/BY# pin when configured as a ready/busy status pin. See "End-of-Write Detection" on page 13 for more information.
FIGURE 1: Functional Block Diagram
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
2
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
PIN DESCRIPTION
Top View CE# SO WP# VSS 1 2 3 4 8 7 6 5 VDD RST#/HOLD# SCK SI
1328.25WF 08-soic-P0.0
FIGURE 2: Pin Assignment for 8-Lead SOIC TABLE 1: Pin Description
Symbol SCK Pin Name Serial Clock Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See "End-of-Write Detection" on page 13 for more information. The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. To reset the operation of the device and the internal logic. The device powers on with RST# pin functionality as default. To temporarily stop serial communication with SPI Flash memory while device is selected. This is selected by an instruction sequence which is detailed in "Reset/Hold Mode" on page 5. To provide power supply voltage: 1.65-1.95V for SST25WF512/010/020
T1.0 1328
SI SO
Serial Data Input Serial Data Output
CE# WP# RST#/HOLD#
Chip Enable Write Protect Reset Hold
VDD VSS
Power Supply Ground
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
3
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
MEMORY ORGANIZATION
The SST25WF512/010/020 SuperFlash memory arrays are organized in uniform 4 KByte with 16 KByte, 32 KByte, and 64 KByte (2Mbit Only) overlay erasable blocks.
used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25WF512/010/020 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25WF512/010/020 are accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is
CE#
MODE 3 MODE 3 MODE 0
SCK SI SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1328 F03.0
HIGH IMPEDANCE
FIGURE 3: SPI Protocol
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
4
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected option where an Enable-Hold instruction enables the Hold mode. Once selected as a hold pin (HOLD#), the RST#/HOLD# pin will be configured as a HOLD# pin, and goes back to RST# pin only after a poweroff and power-on sequence. Reset If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method for resetting the device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be driven low for a minimum of TRST time to reset the device. The SO pin is in high impedance state while the device is in reset. A successful reset will reset the status register to its power-up state. See Table 4 for default power-up modes. A device reset during an active Program or Erase operation aborts the operation and data of the targeted address range may be corrupted or lost due to the aborted erase or program operation. The device exits AAI Programming Mode in progress and places the SO pin in high impedance state.
CE# TRECR TRECP TRECE SCK TRST RST# TRHZ SO
SI
1328 Fx4.0
FIGURE 4: Reset Timing Diagram TABLE 2: Reset Timing Parameters
Symbol TRST TRHZ TRECR TRECP TRECE Parameter Reset Pulse Width Reset to High-Z Output Reset Recovery from Read Reset Recovery from Program Reset Recovery from Erase Min 100 107 100 10 1 Max Units ns ns ns s ms
T2.1328
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
5
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information Hold The Hold operation enables the hold pin functionality of the RST#/HOLD# pin. Once set to hold pin mode, the RST#/ HOLD# pin continues functioning as a hold pin until the device is powered off and then powered on. After a poweroff and power-on, the pin functionality returns to a reset pin (RST#) mode. See "Enable-Hold (EHLD)" on page 19 for detailed timing of the Hold instruction. In the hold mode, serial sequences underway with the SPI Flash memory are paused without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The Hold mode ends when the rising edge of the HOLD# signal coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits Hold mode when the SCK next reaches the active low state. See Figure 5 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, the device returns to standby mode. The device can then be re-initiated with the command sequences listed in Tables 8 and 9. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 5 for Hold timing.
SCK
HOLD# Active Hold Active Hold Active
1328 Fx5.0
FIGURE 5: Hold Condition Waveform
Write Protection
SST25WF512/010/020 provide software Write protection. The Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for the Block-Protection description. Write Protect Pin (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.
TABLE 3: Conditions to execute Write-Status-Register (WRSR) Instruction
WP# L L H BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed
T3.0 1328
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
6
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Status Register
The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or TABLE 4: Software Status Register
Bit 0 1 2 3 4:5 6 Name BUSY WEL BP0 BP1 RES AAI Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 5) Indicate current level of block write protection (See Table 5) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP1 and BP0 are read-only bits 0 = BP1 and BP0 are read/writable Default at Power-up 0 0 1 1 0 0 Read/Write R R R/W R/W N/A R
Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register.
7
BPL
0
R/W
T4.1 1328
Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A `1' for the Busy bit indicates the device is busy with an operation in progress. A `0' indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal Write-Enable-Latch memory. If the WEL bit is set to `1', it indicates the device is Write enabled. If the bit is set to `0' (reset), it indicates the device is not Write enabled and does not accept any Write (Program/Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: * * * * * Device Reset Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Status-Register instructions
Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
* * * *
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
7
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information Block-Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area to be software protected against any memory Write (Program or Erase) operation, see Tables 5-7. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is `0'. Chip-Erase can only be executed if Block-Protection bits are all `0'. After powerup, BP1 and BP0 are set to defaults. See Table 4 for defaults at power-up. Block Protection Lock-Down (BPL) When the WP# pin is driven low (VIL), it enables the BlockProtection-Lock-Down (BPL) bit. When BPL is set to `1', it prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is `Don't Care'. After power-up, the BPL bit is reset to `0'.
TABLE 5: Software Status Register Block Protection for SST25WF512
Status Register Bit Protection Level None 1 (Upper Quarter Memory) 2 (Upper Half Memory) 3 (Full Memory)
1. Default at power-up for BP1 and BP0 is `11'.
Protected Memory Address 512 Kbit None 00C000H-00FFFFH 008000H-00FFFFH 000000H-00FFFFH
T5.1 1328
BP11 0 0 1 1
BP0 0 1 0 1
TABLE 6: Software Status Register Block Protection for SST25WF010
Status Register Bit Protection Level None 1 (Upper Quarter Memory) 2 (Upper Half Memory) 3 (Full Memory)
1. Default at power-up for BP1 and BP0 is `11'.
Protected Memory Address 1 Mbit None 018000H-01FFFFH 010000H-01FFFFH 000000H-01FFFFH
T6.0 1328
BP11 0 0 1 1
BP0 0 1 0 1
TABLE 7: Software Status Register Block Protection for SST25WF020
Status Register Bit Protection Level None 1 (Upper Quarter Memory) 2 (Upper Half Memory) 3 (Full Memory)
1. Default at power-up for BP1 and BP0 is `11'.
Protected Memory Address 2 Mbit None 030000H-03FFFFH 020000H-03FFFFH 000000H-03FFFFH
T7.0 1328
BP11 0 0 1 1
BP0 0 1 0 1
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
8
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
INSTRUCTIONS
Instructions are used to read, write (Erase and Program), and configure the SST25WF512/010/020. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The complete instructions are provided in Tables 8 and 9. All instructions are synchronized off a high-to-low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first.
TABLE 8: Device Operation Instructions for SST25WF512 and SST25WF010
Instruction Read High-Speed Read 4 KByte SectorErase3 32 KByte BlockErase4 Chip-Erase Byte-Program AAI-Word-Program5 RDSR6 EWSR7 WRSR WREN7 WRDI RDID8 EBSY DBSY JEDEC-ID EHLD Description Read Memory Erase 4 KByte of memory array Erase 32 KByte block of memory array Erase Full Memory Array To Program One Data Byte Auto Address Increment Programming Read-Status-Register Enable-Write-Status-Register Write-Status-Register Write-Enable Write-Disable Read-ID Op Code Cycle1 0000 0011b (03H) 0010 0000b (20H) 0101 0010b (52H) 0110 0000b (60H) or 1100 0111b (C7H) 0000 0010b (02H) 1010 1101b (ADH) 0000 0101b (05H) 0110 0000b (50H) 0000 0001b (01H) 0000 0110b (06H) 0000 0100b (04H) 1001 0000b (90H) or 1010 1011b (ABH) Address Cycle(s)2 3 3 3 3 0 3 3 0 0 0 0 0 3 0 0 0 0 Dummy Data Maximum Cycle(s) Cycle(s) Frequency 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 to 1 to 0 0 0 1 2 to 1 to 0 1 0 0 1 to 0 0 3 to 0
T8.0 1328
20 MHz
Read Memory at Higher Speed 0000 1011b (0BH)
40 MHz
Enable SO to output RY/BY# 0111 0000b (70H) status during AAI programming Disable SO to output RY/BY# 1000 0000b (80H) status during AAI programming JEDEC ID read Enable HOLD# pin functionality of the RST#/HOLD# pin 1001 1111b (9FH) 1010 1010b (AAH)
1. 2. 3. 4. 5.
One bus cycle is eight clock periods. Address bits above the most significant bit of each density can be VIL or VIH. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don't care but must be set either at VIL or VIH. 32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don't care but must be set either at VIL or VIH. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0 = 1. 6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 7. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides backward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs. 8. Manufacturer's ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer's ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
(c)2006 Silicon Storage Technology, Inc. S71328-01-000 02/07
9
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information TABLE 9: Device Operation Instructions for SST25WF020
Instruction Read High-Speed Read 4 KByte SectorErase3 32 KByte BlockErase4 64 KByte BlockErase5 Chip-Erase Byte-Program AAI-Word-Program6 RDSR7 EWSR8 WRSR WREN8 WRDI RDID9 EBSY DBSY JEDEC-ID EHLD Description Read Memory Erase 4 KByte of memory array Erase 32 KByte block of memory array Erase 64 KByte block of memory array Erase Full Memory Array To Program One Data Byte Auto Address Increment Programming Read-Status-Register Enable-Write-Status-Register Write-Status-Register Write-Enable Write-Disable Read-ID Op Code Cycle1 0000 0011b (03H) 0010 0000b (20H) 0101 0010b (52H) 1101 1000b (D8H) 0110 0000b (60H) or 1100 0111b (C7H) 0000 0010b (02H) 1010 1101b (ADH) 0000 0101b (05H) 0110 0000b (50H) 0000 0001b (01H) 0000 0110b (06H) 0000 0100b (04H) 1001 0000b (90H) or 1010 1011b (ABH) Address Cycle(s)2 3 3 3 3 3 0 3 3 0 0 0 0 0 3 0 0 0 0 Dummy Data Maximum Cycle(s) Cycle(s) Frequency 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 to 1 to 0 0 0 0 1 2 to 1 to 0 1 0 0 1 to 0 0 3 to 0
T9.0 1328
20 MHz
Read Memory at Higher Speed 0000 1011b (0BH)
40 MHz
Enable SO to output RY/BY# 0111 0000b (70H) status during AAI programming Disable SO to output RY/BY# 1000 0000b (80H) status during AAI programming JEDEC ID read Enable HOLD# pin functionality of the RST#/HOLD# pin 1001 1111b (9FH) 1010 1010b (AAH)
1. 2. 3. 4. 5. 6.
One bus cycle is eight clock periods. Address bits above the most significant bit of each density can be VIL or VIH. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don't care but must be set either at VIL or VIH. 32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don't care but must be set either at VIL or VIH. 64 KByte Block-Erase addresses: use AMS-A16, remaining addresses are don't care but must be set either at VIL or VIH. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0 = 1. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides backward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs. 9. Manufacturer's ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer's ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
10
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Read (20 MHz)
The Read instruction, 03H, supports up to 20 MHz Read. The device outputs a data stream starting from the specified address location. The data stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer automatically increments until the highest memory address is reached. Once the highest memory address is reached, the address pointer automatically increments to the beginning (wraparound) of the address space. For example, for 2 Mbit density, once the data from the address location 3FFFFH is read, the next output is from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits A23-A0. CE# must remain active low for the duration of the Read cycle. See Figure 6 for the Read sequence.
CE#
MODE 3
012345678
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI MSB SO
03
ADD. MSB HIGH IMPEDANCE
ADD.
ADD. N DOUT MSB
1328 Fx6.0
N+1 DOUT
N+2 DOUT
N+3 DOUT
N+4 DOUT
FIGURE 6: Read Sequence
High-Speed-Read (40 MHz)
The High-Speed-Read instruction supporting up to 40 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-SpeedRead cycle. See Figure 7 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wraparound) of the address space. For example, for 2 Mbit density, once the data from address location 3FFFFH is read, the next output will be from address location 000000H.
CE# MODE 3 SCK MODE 0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SI MSB SO
0B
ADD. HIGH IMPEDANCE
ADD.
ADD.
X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT
1328 F07.0
FIGURE 7: High-Speed-Read Sequence
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
11
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction. The ByteProgram instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 8 for the Byte-Program sequence.
CE#
MODE 3
012345
678
15 16
23 24
31 32
39
SCK
MODE 0
SI MSB SO
02
ADD.
ADD.
ADD.
DIN MSB LSB
HIGH IMPEDANCE
1328 F08.0
FIGURE 8: Byte-Program Sequence
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
12
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when multiple bytes or the entire memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI Word Program operation. While within AAI Word Programming sequence, the only valid instructions are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users have three options to determine the completion of each AAI Word program cycle: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the software status register or wait TBP. Refer to End-Of-Write Detection section for details. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI Word Program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23-A0]. Following the addresses, two bytes of data are input sequentially, each one from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0) will be programmed into the initial address [A23-A1] with A0 = 0, the second byte of Data (D1) will be programmed into the initial address [A23-A1] with A0 = 1. CE# must be driven high before the AAI Word Program instruction is executed. The user must check the BUSY status before entering the next valid command. Once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. Check the busy status after WRDI to determine if the device is ready for any command. See Figures 11 and 12 for AAI Word programming sequence. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-EnableLatch bit (WEL = 0) and the AAI bit (AAI = 0). End-of-Write Detection There are three methods to determine completion of a program cycle during AAI Word programming: hardware detection by reading the Serial Output, software detection by polling the BUSY bit in the Software Status Register or wait TBP .
Hardware End-of-Write Detection The Hardware End-of-Write detection method eliminates the overhead of polling the Busy bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the Serial Output (SO) pin to indicate Flash Busy status during AAI Word programming, as shown in Figure 9. The 8-bit command, 70H, must be executed prior to executing an AAI Word-Program instruction. Once an internal programming operation begins, asserting CE# will immediately drive the status of the internal flash status on the SO pin. A `0' indicates the device is busy and a `1' indicates the device is ready for the next instruction. De-asserting CE# will return the SO pin to tristate. The 8-bit command, 80H, disables the Serial Output (SO) pin to output busy status during AAI-Word-program operation, and re-configures SO as an output pin. In this state, the SO pin will function as a normal Serial Output pin. At this time, the RDSR command can poll the status of the Software Status Register. This is shown in Figure 10.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
70 HIGH IMPEDANCE
1328 F09.0
SO
FIGURE 9: Enable SO as Hardware RY/BY# during AAI Programming
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
80 HIGH IMPEDANCE
1328 F10.0
SO
FIGURE 10: Disable SO as Hardware RY/BY# during AAI Programming
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
13
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
CE#
8 0 80 8 16 24 32 40 48 0 8 16 24 0 8 16 24 0 80 8 16
SCK SI WREN AD A A A D0 D1 AD D2 D3 AD
Dn-1 Last 2 Data Bytes Dn WRDI RDSR
Load AAI command, Address, 2 bytes data
WRDI to exit AAI Mode DOUT
SO
Check for Flash Busy Status to load next valid command
Output Status Register Data
Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming
1328 F11.1
FIGURE 11: Auto Address Increment (AAI) Word Program Sequence with Hardware End-of-Write Detection
Check for Flash Busy Status to load next valid command
CE#
8 0 80 8 16 24 32 40 48 0 8 16 24 0 8 16 24 0 8 0 8 16
SCK SI WREN AD A A A D0 D1 AD D2 D3 AD
Dn-1 Dn Last 2 Data Bytes WRDI WRDI to exit AAI Mode DOUT RDSR
Load AAI command, Address, 2 bytes data
SO
Output Status Register Data
Note:
Valid commands during AAI programming: AAI command, Read Status Register command, or WRDI command
1328 F12.1
FIGURE 12: Auto Address Increment (AAI) Word Program Sequence with Software End-of-Write Detection
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
14
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 13 for the Sector-Erase sequence.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
20
ADD.
MSB
ADD.
ADD.
SO
HIGH IMPEDANCE
1326 F13.0
FIGURE 13: Sector-Erase Sequence
32-KByte Block-Erase
The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Significant Address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase. See Figure 14 for the Block-Erase sequences.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
52
ADDR
MSB
ADDR
ADDR
SO
HIGH IMPEDANCE
1328 F14.0
FIGURE 14: 32-KByte Block-Erase Sequence
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
15
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
64-KByte Block-Erase for SST25WF020
The Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23-A0]. Address bits [AMS-A16] (AMS = Most Significant Address) are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase. See Figure 15 for the Block-Erase sequences.
CE#
MODE 3
012345678
15 16
23 24
31
SCK
MODE 0
SI
MSB
D8
ADDR
MSB
ADDR
ADDR
SO
HIGH IMPEDANCE
1328 F15.0
FIGURE 15: 64-KByte Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction is ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 16 for the Chip-Erase sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
60 or C7 HIGH IMPEDANCE
1328 F16.0
SO
FIGURE 16: Chip-Erase Sequence
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
16
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction, 05H, allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 17 for the RDSR instruction sequence.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK SI SO
MODE 0
05
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out
1327 F17.0
FIGURE 17: Read-Status-Register (RDSR) Sequence
Write-Enable (WREN)
The Write-Enable (WREN) instruction, 06H, sets the WriteEnable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed. See Figure 18 for the WREN instruction sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
06 HIGH IMPEDANCE
1328 F18.0
SO
FIGURE 18: Write Enable (WREN) Sequence
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
17
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling any new Write operations from occurring. The WRDI instruction will not terminate any programming operation in progress. Any program operation in progress may continue up to TBP after executing the WRDI instruction. CE# must be driven high before the WRDI instruction is executed. See Figure 19 for the WRDI instruction sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
04 HIGH IMPEDANCE
1328 Fx19.0
SO
FIGURE 19: Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Write-StatusRegister instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. See Figure 20 for EWSR instruction followed by WRSR instruction.
WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to `1'. When the WP# is low, the BPL bit can only be set from `0' to `1' to lock-down the status register, but cannot be reset from `1' to `0'. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to `0' or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to `1' to lock down the status register as well as altering the BP0, and BP1 bits at the same time. See Table 3 for a summary description of WP# and BPL functions.
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command sequence of the
CE#
MODE 3
01234567
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
MODE 0
SI MSB SO
50 or 06 MSB
01 HIGH IMPEDANCE
STATUS REGISTER IN 76543210 MSB
1328 F20.0
FIGURE 20: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence
(c)2006 Silicon Storage Technology, Inc. S71328-01-000 02/07
18
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Enable-Hold (EHLD)
The 8-bit command, AAH, Enable-Hold instruction enables the HOLD functionality of the RST#/HOLD# pin. CE# must remain active low for the duration of the Enable-Hold instruction sequence. CE# must be driven high before the instruction is executed. See Figure 21 for the Enable-Hold instruction sequence.
CE#
MODE 3
01234567
SCK
MODE 0
SI
MSB
AA HIGH IMPEDANCE
1328 F21.0
SO
FIGURE 21: Enable-Hold Sequence
Read-ID
The Read-ID instruction identifies the manufacturer as SST and the device as SST25WF512/010/020. Use the ReadID instruction to identify SST device when using multiple manufacturers in the same socket. See Table 10. The device information is read by executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer's ID is located in address 000000H and the device ID is located in address 000001H. Once the device is in Read-ID mode, the manufacturer's and device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition on CE#. TABLE 10: Product Identification
Address Manufacturer's ID Device ID SST25WF512 SST25WF010 SST25WF020 000000H 000001H 000001H 000001H Data BFH 01H 02H 03H
T10.1328
CE#
MODE 3
012345678
15 16
23 24
31 32
39 40
47 48
55 56
63
SCK
MODE 0
SI
MSB
90 or AB
00
00
ADD
MSB
SO
HIGH IMPEDANCE
MSB
BF
Device ID
BF
Device ID
HIGH IMPEDANCE
Note: 1. The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#. 2. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1328 F22.0
FIGURE 22: Read-ID Sequence
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
19
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as SST25WF512/010/020 and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer's ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. The Device ID is assigned by the manufacturer and contains the type of memory in the first byte and the memory capacity of the device in the second byte. See Figure 23 for the instruction sequence. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output.
CE#
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK
MODE 0
SI HIGH IMPEDANCE
9F
SO
BF
MSB MSB
25
01/02/03
Note:
01 indicates 25WF512, 02 indicates 25WF010, 03 indicates 25WF020
1328 F23.0
FIGURE 23: JEDEC Read-ID Sequence TABLE 11: JEDEC Read-ID Data-Out for SST25WF512
Device ID Manufacturer's ID (Byte 1) BFH Memory Type (Byte 2) 25H Memory Capacity (Byte 3) 01H
T11.0 1328
TABLE 12: JEDEC Read-ID Data-Out for SST25WF010
Device ID Manufacturer's ID (Byte 1) BFH Memory Type (Byte 2) 25H Memory Capacity (Byte 3) 02H
T12.0 1328
TABLE 13: JEDEC Read-ID Data-Out for SST25WF020
Device ID Manufacturer's ID (Byte 1) BFH Memory Type (Byte 2) 25H Memory Capacity (Byte 3) 03H
T13.0 1328
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
20
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range Industrial Industrial (extended)1 Ambient Temp -40C to +85C -40C to +105C VDD 1.65-1.95V 1.70-1.90V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
1. Maximum operating frequency is 20 MHz for Extended Industrial temperature range.
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
21
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
Power-Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 1.8V in less than 180 ms). If the VDD ramp rate is slower than 1V/100 s, a hardware reset is required. The recommended VDD power-up to RESET# high time should be greater than 100 s to ensure a proper reset. See Table 14 and Figures 24 and 25 for more information. TABLE 14: Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE1 Parameter VDD Min to Read Operation VDD Min to Write Operation Minimum 100 100 Units s s
T14.0 1328
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TPU-READ VDD 0V VIH VDD min
RESET#
TRECR CE#
1328 F37.1
Note: See Table 2 on page 5 for TRECR parameter.
FIGURE 24: Power-Up Reset Diagram
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
22
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
VDD
VDD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device.
VDD Min TPU-READ TPU-WRITE
Device fully accessible
Time
1326 F27.0
FIGURE 25: Power-up Timing Diagram
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
23
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
DC Characteristics
TABLE 15: DC Operating Characteristics
Limits Symbol IDDR IDDR2 IDDW ISB ILI ILO VIL VIH VOL VOH Parameter Read Current Read Current Program and Erase Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD 0.2 Min Typ1 9 12 10 2 Max 15 18 15 10 10 10 0.3 Units mA mA mA A A A V V V V Test Conditions CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open CE#=0.1 VDD/0.9VDD@40 MHz, SO=open CE#=VDD CE#=VDD, VIN=VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T15.0 1328
1. Value characterized, not fully tested in production.
TABLE 16: Capacitance (TA = 25C, f=1 Mhz, other pins open)
Parameter COUT CIN1
1
Description Output Pin Capacitance Input Capacitance
Test Condition VOUT = 0V VIN = 0V
Maximum 12 pF 6 pF
T16.0 1328
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 17: Reliability Characteristics
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 100,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T17.0 1328
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
24
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
AC Characteristics
TABLE 18: AC Operating Characteristics
Limits - 20 MHz Symbol FCLK
1
Limits - 40 MHz Min 11 11 Max 40 Units MHz ns ns 5 5 8 8 10 10 100 ns ns ns ns ns ns ns 19 0 2 5 8 8 12 10 ns ns ns ns ns ns ns ns 20 20 0 9 75 75 150 60 ns ns ns ns ms ms ms s
T18.1 1328
Parameter Serial Clock Frequency Serial Clock High Time Serial Clock Low Time Serial Clock Rise Time Serial Clock Fall Time CE# Active Setup Time CE# Active Hold Time CE# Not Active Setup Time CE# Not Active Hold Time CE# High Time CE# High to High-Z Output SCK Low to Low-Z Output Data In Setup Time Data In Hold Time HOLD# Low Setup Time HOLD# High Setup Time HOLD# Low Hold Time HOLD# High Hold Time HOLD# Low to High-Z Output HOLD# High to Low-Z Output Output Hold from SCK Change Output Valid from SCK Sector-Erase Block-Erase Chip-Erase Byte-Program
Min 20 20
Max 20
TSCKH TSCKL TSCKR TSCKF TCES2 TCEH2 TCHS2 TCHH2 TCPH TCHZ TCLZ TDS TDH THLS THHS THLH THHH THZ TLZ TOH TV TSE TBE TSCE TBP
3
5 5 20 20 10 10 100 20 0 5 5 10 10 15 10 20 20 0 20 75 75 150 60
1. Maximum clock frequency for Read instruction, 03H, is 20 MHz 2. Relative to SCK 3. AAI-Word Program TBP maximum specification is also at 60 s maximum time
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
25
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
TCPH CE# TCHH SCK TDS TDH TSCKR TSCKF TCES TCEH TCHS
SI
MSB HIGH-Z
LSB HIGH-Z
1326 F24.0
SO
FIGURE 26: Serial Input Timing Diagram
CE# TSCKH SCK TCLZ SO TV SI
1328 F25.0
TSCKL
TOH MSB LSB
TCHZ
FIGURE 27: Serial Output Timing Diagram
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
26
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
CE# THHH SCK THLH THZ TLZ THLS THHS
SO
SI
HOLD#
1328 F26.0
FIGURE 28: Hold Timing Diagram
VIHT VHT
INPUT? REFERENCE POINTS
VHT
OUTPUT
VLT VILT
VLT
1326 F28.0
AC test inputs are driven at VIHT (0.9VDD) for a logic `1' and VILT (0.1VDD) for a logic `0'. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 29: AC Input/Output Reference Waveforms
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
27
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
PRODUCT ORDERING INFORMATION
SST 25 WF XX XX XXX XXX - 40 - XX - 5I - SA - XX - XX F X Environmental Attribute F1 = non-Pb / non-Sn contact (lead) finish: Nickel plating with Gold top (outer) layer Package Modifier A = 8 leads Package Type S = SOIC 150 mil body width Temperature Range I = Industrial = -40C to +85C Minimum Endurance 5 = 100,000 cycles Operating Frequency 40 = 40 MHz Device Density 512 = 512 Kbit 010 = 1 Mbit 020 = 2 Mbit Voltage W= 1.65-1.95V Product Series 25 = Serial Peripheral Interface flash memory
1. Environmental suffix "F" denotes non-Pb/non-SN solder. SST non-Pb/non-Sn solder devices are "RoHS Compliant".
Valid combinations for SST25WF512 SST25WF512-40-5I-SAF Valid combinations for SST25WF010 SST25WF010-40-5I-SAF Valid combinations for SST25WF020 SST25WF020-40-5I-SAF
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
28
512 Kbit / 1 Mbit / 2 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020
Advance Information
PACKAGING DIAGRAMS
Pin #1 Identifier
TOP VIEW
SIDE VIEW
7 4 places
5.0 4.8 1.27 BSC
0.51 0.33
END VIEW
0.25 0.10 1.75 1.35 0.25 0.19 1.27 0.40 45 7 4 places
4.00 3.80 6.20 5.80
0 8
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
08-soic-5x6-SA-8
1mm
FIGURE 30: 8-Lead Small Outline Integrated Circuit (SOIC) SST Package Code: SA TABLE 19: Revision History
Number 00 01 Description Date Nov 2006 Feb 2007
* * * * * * * * * * *
Initial release of data sheet Removed "Commercial" Temperature Range Added references to Tables 6 and 7 in "Block-Protection (BP1, BP0)" on page 8 Modified EWSR and WREN footnote information and updated EBSY Op Code Cycle in Tables 8 and 9 Re-phrased first paragraph in "Instructions" on page 9 Updated "Byte-Program" on page 12 Clarified SO pin statement in second paragraph of "Hardware End-of-Write Detection" on page 13 Added Industrial (extended) values to Operating Range in "Electrical Specifications" on page 21 Added "Power-Up Specifications" on page 22 Added typical values to Table 15 on page 24 Added contact-lead composition, updated minimum endurance from 10,000 to 100,000 cycles, and changed product valid combinations in "Product Ordering Information" on page 28
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2006 Silicon Storage Technology, Inc. S71328-01-000 02/07
29

▲Up To Search▲

Price & Availability of SST25WF512

	To Download SST25WF512 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .